The TMC10 is the industry's first single chip, wire-speed traffic management co-processor capable of operating at full duplex 10 Gbps and OC-192c rates.

Highly integrated. This highly integrated traffic management solution performs buffer and queue management functions, traffic scheduling, flow control across a switch fabric, congestion management, and statistics for multiprotocol traffic at OC-192c line rates. This allows equipment and network designers to balance congestion control with quality of service parameters for a variety of edge, metro and core network applications.

In addition, the TMC10 includes embedded on-chip full-duplex serializer/deserializer (SERDES) links, with optional ECC for reducing link error rates, for optimal performance and integration efficiency. A rich feature set is provided to maximize carrier-class availability and reliability through support for various fabric redundancy configurations, including N+1, N+2, and 1+1redundancy options, along with zero packet loss fail-over capability.

Flexible. The TMC10 is based on Internet Machines' patent-pending Parallel Channel Architecture (PCA), which allows system designers to develop high-performance multi-gigabit switches that can scale in aggregate and per-port bandwidth capacity, as well as overall system port density, in flexible increments.

Protocol and service independent. The TMC10 allows concurrent traffic management processing of multiprotocol and multiservice traffic.

Interoperable. The TMC10 interoperates with Internet Machines' SE200 protocol-independent switch element or with other switch fabric solutions. To interface to a network processor or other co-processors, the TMC10 supports the Optical Internetworking Forum's SPI-4 Phase 2 Implementation Agreement.

 

  Features and Benefits
  • Single chip, full duplex traffic management processing at 10 Gbps/OC-192c line rates in both ingress and egress directions
  • Up to 1 GB of frame buffer storage on both ingress and egress paths to address the requirements of next generation carrier networking infrastructure
  • Sophisticated carrier-grade traffic management and QoS capabilities provided through flexible queuing and scheduling functions
  • Configurable congestion control mechanisms, including RED (random early discard) and EPD (early packet discard)/PPD (partial packet discard)
  • Supports OIF SPI-4 Phase 2 Interface Implementation Agreement, allowing for glueless connectivity to third party network processors or co-processors
  • Connects directly to Internet Machines' NPE10 network processor to enable a full line card solution for packet processing and forwarding at OC-192c line rates
  • Allows seamless interconnection with switch fabrics based on Internet Machines' SE200 switch element
  • Supports per-flow statistics, as well as other event and diagnostics related statistics Includes support for various fabric redundancy configurations, including N+1, N+2, and 1+1 redundancy options, along with zero packet loss fail-over capability, to maximize carrier-class availability and reliability
  • Incorporates innovative PDU segmentation and reassembly algorithms that eliminate bandwidth inefficiencies in transmitting traffic through fabric subsystems, allowing significant reduction in fabric speedup required to sustain line-rate throughput
  • Allows insertion and extraction of "control" packets via a management interface under external host processor control
  • Memory BIST, JTAG (IEEE P1149.1 standard), and scan function
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Specifications are subject to change without notice. Contact your nearest Internet Machinesrepresentative for additional information.